As transistor dimensions continue to shrink with each new process technology, read stability of a six transistor (6T) Static Random Access Memory (SRAM) bit-cell becomes a challenging issue for SRAM design. Various read assist techniques are used to maintain the read stability of the SRAM bit-cell. One method is to reduce the voltage at a word-line driver during a normal read or write operation which weakens the transfer gate of the 6T bit-cell and aids bit-cell read stability. However, traditional methods for under driving the word-line results in high dynamic power dissipation, electro-migration, and reliability issues with read assist circuits, etc.